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D a t a S he et , V 1. 0, J u l y 2 00 3
HYS[64/72]D64x20HU-[5/6]-C HYS[64/72]D32x00HU-[5/6]-C H Y S 64 D 1 6 x 0 1 H U - [ 5 / 6 ] - C
1 8 4 - P i n U n b u f f er e d D u a l - I n- L i n e M e m o r y M o d u l es Reg DIMM DDR SDRAM
M e m or y P r o du c t s
Never
stop
thinking.
Edition 2003-07 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2003. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
D a t a S he et , V 1. 0, J u l y 2 00 3
HYS[64/72]D64x20HU-[5/6]-C HYS[64/72]D32x00HU-[5/6]-C H Y S 64 D 1 6 x 0 1 H U - [ 5 / 6 ] - C
1 8 4 - P i n U n b u f f er e d D u a l - I n- L i n e M e m o r y M o d u l es Reg DIMM DDR SDRAM
M e m or y P r o du c t s
Never
stop
thinking.
HYS[64/72]D64x20HU-[5/6]-C, HYS[64/72]D32x00HU-[5/6]-C, HYS64D16x01HU-[5/6]-C Revision History: Previous Version: Page all V1.0 - 2003-07
Subjects (major changes since last revision) new data sheet template
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Template: mp_a4_v2.0_2003-06-06.fm
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C Unbuffered DDR SDRAM Modules
Table of Contents 1 1.1 1.2 2 3 3.1 3.2 3.3 4 5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current Conditions and Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17 19 22
SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Data Sheet
5
V1.0, 2003-07
184-Pin Unbuffered Dual-In-Line Memory Modules Reg DIMM
HYS[64/72]D64x20HU-[5/6]-C HYS[64/72]D32x00HU-[5/6]-C HYS64D16x01HU-[5/6]-C
1
1.1
* * * * * * * * * * * * *
Overview
Features
184-Pin Unbuffered Dual-In-Line Memory Modules (ECC and non-parity) for PC and Server main memory applications One rank 16M x 64, 32M x 64, 32M x 72 and two ranks 64M x 64, 64M x 72 organization JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5V (0.2V) power supply Built with 256 Mbit DDR SDRAM in P-TSOPII-66-1 package Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh All inputs and outputs SSTL_2 compatible Serial Presence Detect with E2PROM JEDEC standard MO-206 form factor: 133.35 mm x 31.75 mm x 4.00 mm max. Jedec standard reference layout Gold plated contacts DDR400 Speed Grade supported Lead-free Performance -5 DDR400B PC3200-3033 @ CL = 3 @ CL = 2.5 @ CL = 2 -6 DDR333B PC2700-2533 166 166 133 Unit - - MHz MHz MHz
Table 1
Part Number Speed Code Module Speed Grade Component Module max. Clock Frequency
fCK3 fCK2.5 fCK2
200 166 133
1.2
Description
The HYS[64/72]D64x20HU-[5/6]-C, HYS[64/72]D32x00HU-[5/6]-C, and HYS64D16x01HU-[5/6]-C are industry standard 184-Pin Unbuffered Dual-In-Line Memory Modules (Reg DIMM) organized as 16M x 64, 32M x 64 and 64M x 64 for non-parity and 32M x 72 and 64M x 72 for ECC main memory applications. The memory array is designed with 256Mbit Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the printed circuit board. The DIMMs feature serial presence detect (SPD) based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer
Data Sheet
6
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C Unbuffered DDR SDRAM Modules
Overview Table 2 Type PC3200 (CL=3) HYS64D16301HU-5-C HYS64D32300HU-5-C HYS72D32300HU-5-C HYS64D64320HU-5-C HYS72D64320HU-5-C PC2700 (CL=2.5) HYS64D16301HU-6-C HYS64D32300HU-6-C HYS72D32300HU-6-C HYS64D64320HU-6-C HYS72D64320HU-6-C PC2700U-25330-C0 PC2700U-25330-A0 PC2700U-25330-A0 PC2700U-25330-B0 PC2700U-25330-B0 one rank 128MB DIMM one rank 256MB DIMM one rank 256MB ECC-DIMM two ranks 512MB DIMM 256 Mbit (x 16) 256 Mbit (x 8) 256 Mbit (x 8) 256 Mbit (x 8) PC3200U-30330-C0 PC3200U-30330-A0 PC3200U-30330-A0 PC3200U-30330-B0 PC3200U-30330-B0 one rank 128MB DIMM one rank 256MB DIMM one rank 256MB ECC-DIMM two ranks 512MB DIMM 256 Mbit (x 16) 256 Mbit (x 8) 256 Mbit (x 8) 256 Mbit (x 8) Ordering Information Compliance Code Description SDRAM Technology
two ranks 512MB ECC-DIMM 256 Mbit (x 8)
two ranks 512MB ECC-DIMM 256 Mbit (x 8)
Note: All part numbers end with a place code designating the silicon-die revision. Reference information available on request. Example: HYS72D32000HU-6-C, indicating rev. C dies are used for SDRAM components. The Compliance Code is printed on the module labels describing the speed sort (for example "PC2700"), the latencies and SPD code definition (for example "20330" means CAS latency of 2.0 clocks, RCD1) latency of 3 clocks, Row Precharge latency of 3 clocks, and JEDEC SPD code definiton version 0), and the Raw Card used for this module.
1) RCD: Row-Column-Delay
Data Sheet
7
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C Unbuffered DDR SDRAM Modules
Pin Configuration
2
Table 3 Symbol A0 - A12 BA0, BA1 DQ0 - DQ63 CB0 - CB7
Pin Configuration
Pin Definitions and Functions Type1) I I I/O I/O I I I/O I I I I/O I PWR GND PWR PWR AI PWR I I/O I NC Function Address Inputs Bank Selects Data Input/Output Check Bits (x 72 organization only) Command Inputs Clock Enable SDRAM low data strobes SDRAM clock (positive lines) SDRAM clock (negative lines) SDRAM low data mask/ high data strobes Chip Selects for Rank0 and Rank1 Power (+2.5 V) Ground I/O Driver power supply VDD Indentification flag I/O reference supply Serial EEPROM power supply Serial bus clock Serial bus data line slave address select Not Connected
RAS, CAS, WE CKE0 - CKE1 DQS0 - DQS8 CK0 - CK2, CK0 - CK2 DM0 - DM8 DQS9 - DQS17 S0, S1 VDD VSS VDDQ VDDID VREF VDDSPD SCL SDA SA0 - SA2 NC
1) I: Input; O: Output; I/O: bidirectional In-/Output; AI: Analog Input; PWR: Power Supply; GND: Signal Ground; NC: Not Connected
Note: S1 and CKE1 are used on two rank modules only
Data Sheet
8
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C Unbuffered DDR SDRAM Modules
Pin Configuration Table 4 Frontside PIN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Symbol PIN# 48 49 50 51 52 Symbol A0 NC / CB2 Pin Configuration Backside PIN# 93 94 95 96 97 98 99 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 DQ32 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 Symbol PIN# 140 141 142 143 144 Symbol NC / DM8/DQS17 A10 NC / CB6
VREF
DQ0
VSS
DQ4 DQ5
VSS
DQ1 DQS0 DQ2
VSS
NC / CB3 BA1 Key
VDDQD
DM0/DQS9 DQ6 DQ7
VDDQD
NC / CB7 Key
VDD
DQ3 NC NC
VSS
NC NC NC
145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
VSS
DQ36 DQ37
VDDQ
DQ33 DQS4 DQ34
VSS
DQ8 DQ9 DQS1
VDD
DM4/DQS13 DQ38 DQ39
VDDQ
DQ12 DQ13 DM1/DQS10
VSS
BA0 DQ35 DQ40
VDDQ
CK1 CK1
VSS
DQ44 RAS DQ45
VDD
DQ14 DQ15 CKE1
VDDQ
WE DQ41 CAS
VSS
DQ10 DQ11 CKE0
VDDQ
S0 S1 DM5/DQS14
VDDQ
NC (BA2) DQ20 NC / A12
VSS
DQS5 DQ42 DQ43
VDDQ
DQ16 DQ17 DQS2
VSS
DQ46 DQ47 NC
VSS
DQ21 A11 DM2/DQS11
VDD
NC DQ48 DQ49
VSS
A9 DQ18 A7
VDDQ
DQ52 DQ53 NC (A13)
VDD
DQ22 A8 DQ23
VSS
CK2 CK2
VDDQ
DQ19 A5 DQ24
VDD
DM6/DQS15 DQ54 DQ55
VDDQ
DQS6 DQ50 DQ51
VSS
A6 DQ28 DQ29
VSS
DQ25 DQS3 A4
VDDQ
NC DQ60 DQ61
VSS VDDID
DQ56 DQ57
VDDQ
DM3/DQS12 A3 DQ30
VDD
DQ26
VSS
V1.0, 2003-07
Data Sheet
9
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C Unbuffered DDR SDRAM Modules
Pin Configuration Table 4 Frontside PIN# 40 41 42 43 44 45 46 47 Symbol DQ27 A2 PIN# 85 86 87 88 89 90 91 92 Symbol Pin Configuration (cont'd) Backside PIN# 132 133 134 135 136 137 138 139 Symbol PIN# 177 178 179 180 181 182 183 184 Symbol DM7/DQS16 DQ62 DQ63
VDD
DQS7 DQ58 DQ59
VSS
DQ31 NC / CB4 NC / CB5
VSS
A1 NC / CB0 NC / CB1
VDDQ
SA0 SA1 SA2
VSS
NC SDA SCL
VDDQ
CK0 CK0
VDD
NC / DQS8
VSS
VDDSPD
Note: Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC ("not connected") on x 64 organised non-ECC modules. Table 5 Density 128MB 256MB 256MB 512MB 512MB Address Format Organization Memory SDRAMs # of # of row/bank/ Ranks SDRAMs columns bits 16M x 64 32M x 64 32M x 72 64M x 64 64M x 72 1 1 1 2 2 16M x 1 4 6 32M x 8 8 32M x 8 9 32M x 8 16 32M x 8 18 13/2/10 13/2/11 13/2/11 13/2/11 13/2/11 Refresh 8K 8K 8K 8K 8K Period Interval 64 ms 64 ms 64 ms 64 ms 64 ms 7.8 s 7.8 s 7.8 s 7.8 s 7.8 s
Data Sheet
10
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C Unbuffered DDR SDRAM Modules
Pin Configuration
S0 DQS1 DM1/DQS10
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 S
DQS5 DM5/DQS14
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
S
D0
D2
DQS0 DM0/DQS9
DQS4 DM4/DQS13
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQS2 DM2/DQS11
LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
S
DQS7 DM7/DQS16
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
D1
DQS6 DM6/DQS15
LDQS LDM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 UDQS UDM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15
S
D3
Serial PD SCL VDD SPD VDD /VDDQ VREF VSS VDDID SPD D0 - D3 D0 - D3 D0 - D3 Strap: see Note 4 WP A0 SA0 A1 SA1 A2 SA2 SDA
* Clock Wiring Clock SDRAMs Input *CK0/CK0 *CK1/CK1 *CK2/CK2 NC 2 SDRAMs 2 SDRAMs
* Wire per Clock Loading Table/Wiring Diagrams
BA0 - BA1 A0 - A13 RAS CAS CKE0 WE
BA0-BA1: SDRAMs D0 - D3 A0-A13: SDRAMs D0 - D3 RAS: SDRAMs D0 - D3 CAS: SDRAMs D0 - D3 CKE: SDRAMs D0 - D3 WE: SDRAMs D0 - D3
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 ohms 5%. 4. VDDID strap connections (for memory device VDD, VDDQ ): STRAP OUT (OPEN): V DD = VDDQ STRAP IN (VSS): V DD VDDQ 5. BAx, Ax, RAS, CAS, WE resistors: 7.5 ohms 5%
Figure 1
Block Diagram - One Rank 16M x 64 DDR SDRAM DIMM HYS64D16301GU using x 16 organized SDRAMs
Data Sheet
11
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C Unbuffered DDR SDRAM Modules
Pin Configuration
DQS0 DM0/DQS9
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
S0
DQS
DQS4 DM4/DQS13
S DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
D4
DQS1 DM1/DQS10
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS5 DM5/DQS14
D1
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D5
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS6 DM6/DQS15
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D2
D6
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS7 DM7/DQS16
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D3
D7
Serial PD SCL WP A0 SA0 A1 SA1 A2 SA2 SDA
* Clock Wiring Clock SDRAMs Input *CK0/CK0 *CK1/CK1 *CK2/CK2 2 SDRAMs 3 SDRAMs 3 SDRAMs
* Wire per Clock Loading Table/Wiring Diagrams BA0 - BA1 A0 - A13 RAS CAS CKE0 WE BA0-BA1: SDRAMs D0 - D7 A0-A13: SDRAMs D0 - D7 RAS: SDRAMs D0 - D7 CAS: SDRAMs D0 - D7 CKE: SDRAMs D0 - D7 WE: SDRAMs D0 - D7 VDD SPD VDD/VDDQ VREF VSS VDDID SPD D0 - D7 D0 - D7 D0 - D7 Strap: see Note 4
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 ohms 5% 4. VDDID strap connections (for memory device VDD , V DDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): VDD VDDQ . 5. BAx, Ax, RAS, CAS, WE resistors: 5.1 ohms +5%
Figure 2
Block Diagram - One Rank 32M x 64 DDR-I SDRAM DIMM HYS64D32x 00GU / HYS64D32300EU using x 8 organized SDRAMs
Data Sheet
12
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C Unbuffered DDR SDRAM Modules
Pin Configuration
S1 S0 DQS0 DM0/DQS9
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS4 DM4/DQS13
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D0
D8
D4
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S
DQS
D12
DQS1 DM1/DQS10
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS5 DM5/DQS14
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D1
D9
D5
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S
DQS
D13
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS6 DM6/DQS15
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D2
D10
D6
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S
DQS
D14
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS7 DM7/DQS16
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D3
D11
D7
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S
DQS
D15
VDD SPD VDD/VDDQ VREF VSS VDDID
SPD D0 - D15 D0 - D15 D0 - D15 Strap: see Note 4 SCL WP A0 SA0 SDA A1 SA1 A2 SA2 Serial PD
BA0 - BA1 A0 - A13 CKE1 RAS CAS CKE0 WE
BA0-BA1: SDRAMs D0 - D15 A0-A13: SDRAMs D0 - D15 CKE: SDRAMs D8 - D15 RAS: SDRAMs D0 - D15 CAS: SDRAMs D0 - D15 CKE: SDRAMs D0 - D7 WE: SDRAMs D0 - D15
* Clock Wiring Clock SDRAMs Input *CK0/CK0 *CK1/CK1 *CK2/CK2 4 SDRAMs 6 SDRAMs 6 SDRAMs
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 ohms 5%. 4. VDDID strap connections (for memory device VDD, V DDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): V DD VDDQ 5. BAx, Ax, RAS, CAS, WE resistors: 3 ohms +5%
* Wire per Clock Loading Table/Wiring Diagrams
Figure 3
Block Diagram - Two Rank 64M x 64 DDR-I SDRAM DIMM HYS64D64x 20GU using x 8 Organized SDRAMs
Data Sheet
13
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C Unbuffered DDR SDRAM Modules
Pin Configuration
DQS0 DM0/DQS9
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
S0
DQS
DQS4 DM4/DQS13
S DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
D4
DQS1 DM1/DQS10
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS5 DM5/DQS14
D1
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D5
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS6 DM6/DQS15
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D2
D6
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS7 DM7/DQS16
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D3
D7
DQS8 DM8/DQS17
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
Serial PD SCL WP A0 SA0 SDA A1 SA1 A2 SA2
* Clock Wiring Clock SDRAMs Input *CK0/CK0 *CK1/CK1 *CK2/CK2 3 SDRAMs 3 SDRAMs 3 SDRAMs
D8
* Wire per Clock Loading Table/Wiring Diagrams
BA0 - BA1 A0 - A13 RAS CAS CKE0 WE
BA0-BA1: SDRAMs D0 - D8 A0-A13: SDRAMs D0 - D8 RAS: SDRAMs D0 - D8 CAS: SDRAMs D0 - D8 CKE: SDRAMs D0 - D8 WE: SDRAMs D0 - D8 VDDSPD VDD/VDDQ VREF VSS VDDID
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be SPD maintained as shown. D0 - D8 3. DQ, DQS, DM/DQS resistors: 22 ohms 5%. 4. VDDID strap connections D0 - D8 (for memory device VDD, V DDQ ): D0 - D8 STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): V DD VDDQ. Strap: see Note 4 5. BAx, Ax, RAS, CAS, WE resistors: 5.1 ohm +5%
Figure 4
Block Diagram - One Rank 32M x 72 DDR-I SDRAM DIMM HYS72D32x 00GU using x 8 organized SDRAMs
Data Sheet
14
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Pin Configuration
S1 S0 DQS0 DM0/DQS9
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS4 DM4/DQS13
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D0
D9
D4
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S
DQS
D13
DQS1 DM1/DQS10
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS5 DM5/DQS14
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D1
D10
D5
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S
DQS
D14
DQS2 DM2/DQS11
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS6 DM6/DQS15
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D2
D11
D6
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S
DQS
D15
DQS3 DM3/DQS12
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
DQS7 DM7/DQS16
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
D3
D12
D7
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
S
DQS
D16
DQS8 DM8/DQS17
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
VDD SPD VDD/VDDQ
DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S DQS
SPD D0 - D17 D0 - D17 D0 - D17
VREF VSS VDDID Strap: see Note 4
* Clock Wiring Clock SDRAMs Input *CK0/CK0 *CK1/CK1 *CK2/CK2 6 SDRAMs 6 SDRAMs 6 SDRAMs
D8
D17
BA0 - BA1 A0 - A13 CKE1 RAS CAS CKE0 WE
BA0-BA1: SDRAMs D0 - D17 A0-A13: SDRAMs D0 - D17 CKE: SDRAMs D9 - D17 RAS: SDRAMs D0 - D17 CAS: SDRAMs D0 - D17 CKE: SDRAMs D0 - D8 WE: SDRAMs D0 - D17 Serial PD SCL WP A0 SA0 A1 SA1 A2 SA2
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 ohms 5%. 4. VDDID strap connections SDA (for memory device VDD, V DDQ): STRAP OUT (OPEN): VDD = VDDQ STRAP IN (VSS): V DD VDDQ 5. BAx, Ax, RAS, CAS, WE resistors: 3 ohms +5%
* Wire per Clock Loading Table/Wiring Diagrams
Figure 5
Block Diagram - Two Rank 64M x 72 DDR-I SDRAM DIMM HYS72D64x 20GU using x 8 Organized SDRAMs
Data Sheet
15
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HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C Unbuffered DDR SDRAM Modules
Pin Configuration
6 DRAM Loads
DRAM1
DRAM2 CK R = 120 5% DIMM Connector CK DRAM3 4 DRAM Loads
DRAM4 DRAM5
DRAM1
DRAM2 DRAM6 R = 120 5% DIMM Connector Cap.
Cap. 3 DRAM Loads DRAM1 DRAM5
Cap. R = 120 5% DIMM Connector DRAM3
DRAM6
Cap. 2 DRAM Loads DRAM5 DRAM1
Cap. DIMM Connector Cap.
Cap. R = 120 5% Cap.
1 DRAM Loads
Cap. DRAM5
Cap. R = 120 5% DIMM Connector DRAM3
Cap.
Cap. Cap.
Cap. Cap. = 1/2 DDR SDRAM input capacitance; 1.0 pF 20%
Figure 6
Clock Net Wiring
Data Sheet
16
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HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C Unbuffered DDR SDRAM Modules
Electrical Characteristics
3
3.1
Table 6 Parameter
Electrical Characteristics
Operating Conditions
Absolute Maximum Ratings Symbol min. Values typ. - - - - - - 1 50 max. -0.5 -1 -1 -1 0 -55 - - Unit Note/ Test Condition V V V V C C W mA - - - - - - - -
Voltage on I/O pins relative to VSS Voltage on inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating temperature (ambient) Storage temperature (plastic) Power dissipation (per SDRAM component) Short circuit output current
VIN, VOUT VIN VDD VDDQ TA TSTG
PD
VDDQ +
0.5 +3.6 +3.6 +3.6 +70 +150 - -
IOUT
Attention: Permanent damage to the device may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. Table 7 Parameter Device Supply Voltage Electrical Characteristics and DC Operating Conditions Symbol Min. 2.3 2.5 2.3 2.5 2.3 0 Values Typ. 2.5 2.6 2.5 2.6 2.5 Max. 2.7 2.7 2.7 2.7 3.6 0 V V V V V V Unit Note/Test Condition 1)
VDD Device Supply Voltage VDD Output Supply Voltage VDDQ Output Supply Voltage VDDQ EEPROM supply voltage VDDSPD Supply Voltage, I/O Supply VSS, Voltage VSSQ VREF Input Reference Voltage Input Reference Voltage VREF
I/O Termination Voltage (System)
fCK 166 MHz fCK > 166 MHz 2) fCK 166 MHz 3) fCK > 166 MHz 2)3)
-- --
0.49 x VDDQ 0.5 x VDDQ 0.51 x VDDQ V
VDDQ / 2 - 50 mV VREF - 0.04 VREF + 0.15
-0.3 -0.3 0.36
VDDQ
/2
VDDQ / 2
+ 50 mV
V
fCK 166 MHz 4) fCK > 166 MHz 2)4)
5)
VTT
VREF + 0.04 V VDDQ + 0.3 V VREF - 0.15 V VDDQ + 0.3 V VDDQ + 0.6
V
Input High (Logic1) Voltage VIH(DC) Input Low (Logic0) Voltage VIL(DC) Input Voltage Level, CK and CK Inputs Input Differential Voltage, CK and CK Inputs
8) 8) 8)
VIN(DC) VID(DC)
8)6)
Data Sheet
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HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C Unbuffered DDR SDRAM Modules
Electrical Characteristics Table 7 Parameter VI-Matching Pull-up Current to Pull-down Current Input Leakage Current Electrical Characteristics and DC Operating Conditions (cont'd) Symbol Min. VIRatio 0.71 Values Typ. Max. 1.4 --
7)
Unit Note/Test Condition 1)
II
-2
2
A
Any input 0 V VIN VDD; All other pins not under test = 0 V 8)9) DQs are disabled; 0 V VOUT VDDQ 8)
Output Leakage Current Output High Current, Normal Strength Driver Output Low Current, Normal Strength Driver
1) 0 C TA 70 C
IOZ IOH IOL
-5 -- 16.2
5 -16.2 --
A mA mA
VOUT = 1.95 V 8) VOUT = 0.35 V 8)
2) DDR400 conditions apply for all clock frequencies above 166 MHz 3) Under all conditions, VDDQ must be less than or equal to VDD. 4) Peak to peak AC noise on VREF may not exceed 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. 5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 6) VID is the magnitude of the difference between the input level on CK and the input level on CK. 7) The ration of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 8) Inputs are not recognized as valid until VREF stabilizes. 9) Values are shown per DDR SDRAM component
Data Sheet
18
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C Unbuffered DDR SDRAM Modules
Electrical Characteristics
3.2
Table 8 Parameter
Current Conditions and Specification
IDD Conditions
Symbol
Operating Current 0 one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current 1 one bank; active/read/precharge; Burst Length = 4; see component data sheet. Precharge Power-Down Standby Current all banks idle; power-down mode; CKE VIL,MAX Precharge Floating Standby Current CS VIH,,MIN, all banks idle; CKE VIH,MIN; address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current CS VIHMIN, all banks idle; CKE VIH,MIN; VIN = VREF for DQ, DQS and DM; address and other control inputs stable at VIH,MIN or VIL,MAX. Active Power-Down Standby Current one bank active; power-down mode; CKE VILMAX; VIN = VREF for DQ, DQS and DM. Active Standby Current one bank active; CS VIH,MIN; CKE VIH,MIN; tRC = tRAS,MAX; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. Operating Current Read one bank active; Burst Length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA Operating Current Write one bank active; Burst Length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B Auto-Refresh Current tRC = tRFCMIN, distributed refresh Self-Refresh Current CKE 0.2 V; external clock on Operating Current 7 four bank interleaving with Burst Length = 4; see component data sheet.
IDD0
IDD1 IDD2P IDD2F
IDD2Q
IDD3P IDD3N
IDD4R
IDD4W
IDD5 IDD6 IDD7
Data Sheet
19
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C Unbuffered DDR SDRAM Modules
Electrical Characteristics
Table 9
IDD Specification (PC2700, -6)
HYS64D16301HU-6-C HYS64D32000HU-6-C HYS72D32000HU-6-C HYS64D64020HU-6-C HYS72D64020HU-6-C Unit Note 1)2)
Part Number & Organization
128MB x 64 1 Rank -6 typ. 260 320 14 100 68 44 136 340 360 540 5.6 820 max. 300 380 18 340 96 60 160 400 440 640 11.2 960
256MB x 64 1 Rank -6 typ. 480 560 28 200 136 88 256 560 600 1080 11.2 1440 max. 600 680 36 240 192 120 304 680 720 1280 22.4 1720
256MB x 72 1 Rank -6 typ. 540 630 31.5 225 153 99 288 630 675 1215 12.6 1620 max. 675 765 40.5 270 216 135 342 765 810 1440 25.2 1935
512MB x 64 2 Ranks -6 typ. 736 816 56 400 272 176 512 816 856 1336 44.8 1696 max. 904 984 72 480 384 240 608 984 1024 1584 22.4 2024
512MB x 72 2 Ranks -6 typ. 828 918 63 450 306 198 576 918 963 1503 25.2 1908 max. 1017 1107 81 540 432 270 684 1107 1152 1782 25.2 2277 mA mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5) 3)4)
Symbol
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ loading capacity. 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows: m x IDDx[component] + n x IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included in the calculations (see note 1) 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx[component]
Data Sheet
20
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Electrical Characteristics
Table 10
IDD Specification (PC3200, -5)
HYS64D16301HU-5-C HYS64D32000HU-5-C HYS72D32000HU-5-C HYS64D64020HU-5-C HYS72D64020HU-5-C Unit Note 1)2)
Part Number & Organization
128MB x 64 1 Rank -5 typ. 280 340 14 120 76 48 152 400 420 600 6 900 max. 340 420 18 144 104 64 184 480 520 720 11.6 1060
256MB x 64 1 Rank -5 typ. 560 640 28 240 152 96 288 680 720 1200 12 1600 max. 640 760 36 288 208 128 344 800 840 1440 23.2 1920
256MB x 72 1 Rank -5 typ. 630 720 31.5 270 171 108 324 765 810 1350 13.5 1800 max. 720 855 40.5 324 234 144 387 900 945 1620 26.1 2160
512MB x 64 2 Ranks -5 typ. 848 928 56 480 304 192 576 968 1008 1488 24 1888 max. 984 1104 72 576 416 256 688 1144 1184 1784 46.4 2264
512MB x 72 2 Ranks -5 typ. 954 1044 63 540 342 216 648 1089 1134 1674 27 2124 max. 1107 1242 81 648 468 288 774 1287 1332 2007 52.2 2547 mA mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5) 3)4)
Symbol
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ loading capacity. 2) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows: m x IDDx[component] + n x IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules 4) DQ I/O (IDDQ) currents are not included in the calculations (see note 1) 5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) x IDDx[component]
Data Sheet
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Electrical Characteristics
3.3
Table 11 Parameter
AC Characteristics
AC Timing - Absolute Specifications -6/-5 Symbol Min. -6 DDR333 Max. +0.7 +0.6 0.55 0.55 12 12 12 -- -- -- -- +0.7 +0.7 1.25 +0.40 +0.45 +0.50 +0.55 -- -- -- -- -- -- 0.60 -- -- -- -- -- 1.1 Min. -0.6 -0.5 0.45 0.45 5 6 7.5 0.4 0.4 tbd tbd -0.6 -0.6 0.75 -- -- -- -- -5 DDR400B Max. +0.6 +0.5 0.55 0.55 12 12 12 -- -- -- -- +0.6 +0.6 1.25 +0.40 +0.40 +0.50 +0.50 -- -- -- -- -- -- 0.60 -- -- -- -- -- 1.1 ns ns
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
Unit Note/ Test Condition 1)
DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width Clock Half Period Clock cycle time
tAC tDQSCK tCH tCL tHP tCK
-0.7 -0.6 0.45 0.45 6 6 7.5
tCK tCK
ns ns ns ns ns ns ns ns ns
min. (tCL, tCH)
min. (tCL, tCH) ns
CL = 3.0 2)3)4)5) CL = 2.5 2)3)4)5) CL = 2.0 2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5)6)
DQ and DM input hold time DQ and DM input setup time Control and Addr. input pulse width (each input) DQ and DM input pulse width (each input) Data-out high-impedance time from CK/CK Data-out low-impedance time from CK/CK Write command to 1st DQS latching transition DQS-DQ skew (DQS and associated DQ signals) Data hold skew factor DQ/DQS output hold time DQS input low (high) pulse width (write cycle)
tDH tDS tIPW tDIPW tHZ tLZ tDQSS tDQSQ tQHS tQH
0.45 0.45 2.2 1.75 -0.7 -0.7 0.75 -- -- -- --
2)3)4)5)6) 2)3)4)5)7) 2)3)4)5)7) 2)3)4)5)
tCK
ns ns ns ns ns
TFBGA 2)3)4)5) TSOPII 2)3)4)5) TFBGA 2)3)4)5) TSOPII 2)3)4)5)
2)3)4)5)
tHP - tQHS
0.35 0.2 0.2 2 0 0.40 0.25 0.75 0.8
tHP - tQHS
0.35 0.2 0.2 2 0 0.40 0.25 0.6 0.7 0.6 0.7 0.9
tDQSL,H DQS falling edge to CK setup time (write cycle) tDSS DQS falling edge hold time from CK (write tDSH
cycle) Mode register set command cycle time Write preamble setup time Write postamble Write preamble Address and control input setup time
tCK tCK tCK tCK
ns
2)3)4)5) 2)3)4)5) 2)3)4)5)
tMRD tWPRES tWPST tWPRE tIS
2)3)4)5) 2)3)4)5)8) 2)3)4)5)9) 2)3)4)5)
tCK tCK
ns ns ns ns
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10)
Address and control input hold time
tIH
0.75 0.8
fast slew rate
3)4)5)6)10)
slow slew rate
3)4)5)6)10) 2)3)4)5)
Read preamble Data Sheet
tRPRE
22
0.9
tCK
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Electrical Characteristics Table 11 Parameter AC Timing - Absolute Specifications -6/-5 (cont'd) Symbol Min. Read postamble -6 DDR333 Max. 0.60 -- -- -- -- -- -- -- Min. 0.40 55 65 15 15 15 10 15 -5 DDR400B Max. 0.60 -- -- -- -- -- -- -- Unit Note/ Test Condition 1)
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
tRPST Active to Precharge command tRAS Active to Active/Auto-refresh command period tRC Auto-refresh to Active/Auto-refresh command tRFC
period Active to Read or Write delay Precharge command period Active to Autoprecharge delay Active bank A to Active bank B command Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Exit self-refresh to non-read command Exit self-refresh to read command Average Periodic Refresh Interval
0.40 42 60 72 18 18 18 12 15
tCK
ns ns ns ns ns ns ns
70E+3 40
70E+3 ns
tRCD tRP tRAP tRRD tWR tDAL tWTR tXSNR tXSRD tREFI
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)11)
tCK
1 75 200 -- -- -- -- 7.8 1 75 200 -- -- -- -- 7.8
tCK
ns
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)12)
tCK
s
1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V (DDR333); VDDQ = 2.6 V 0.1 V, VDD = +2.6 V 0.1 V (DDR400) 2) Input slew rate 1 V/ns for DDR400, DDR333 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) These parameters guarantee device timing, but they are not necessarily tested on each device. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VOH(ac) and VOL(ac). 11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
23
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SPD Contents
4
Table 12
SPD Contents
SPD Codes for PC2700 Modules "-6" HYS64D16301HU-6-C HYS64D32300HU-6-C HYS72D32300HU-6-C HYS64D64320HU-6-C HYS72D64320HU-6-C 512MB x 72 -6 HEX 80 08 07 0D 0A 02 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 20 V1.0, 2003-07
Part Number & Organization
128MB 256MB 256MB 512MB x 64 -6 HEX 80 08 07 0D 09 01 40 00 04 60 70 00 82 10 00 01 0E 04 0C 01 02 20 x 64 -6 HEX 80 08 07 0D 0A 01 40 00 04 60 70 00 82 08 00 01 0E 04 0C 01 02 20 x 72 -6 HEX 80 08 07 0D 0A 01 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 20 x 64 -6 HEX 80 08 07 0D 0A 02 40 00 04 60 70 00 82 08 00 01 0E 04 0C 01 02 20
1 Rank 1 Rank 1 Rank 2Ranks 2Ranks
Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM # of Row Addresses # Number of Column Addresses # of DIMM Banks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tAC SDRAM @ CLmax (Byte 18) [ns] DIMM Configuration Type (non- / ECC) Refresh Rate Primary SDRAM width Error Checking SDRAM width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM CAS Latency CS Latency WE (Write) Latency DIMM Attributes 128 256
Memory Type DDR-I = 07h DDR SDRAM 13 9/10 1/2 x 64/x 72 0 SSTL_2.5 0.75 ns non-ECC/ECC Self-Refresh 7.8 s x 16/ x 8 na/ x 8
tCK @ CLmax (Byte 18) [ns] 6 ns
tCCD = 1 CLK
2, 4 & 8 4 CAS latency = 2 & 2.5 CS latency = 0 Write latency = 1 unbuffered
Data Sheet
24
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C Unbuffered DDR SDRAM Modules
SPD Contents Table 12 SPD Codes for PC2700 Modules "-6" (cont'd) HYS64D16301HU-6-C HYS64D32300HU-6-C HYS72D32300HU-6-C HYS64D64320HU-6-C HYS72D64320HU-6-C 512MB x 72 -6 HEX C1 75 70 00 00 48 30 48 2A 40 75 75 45 45 00 3C 48 30 2D 55 00 00 14 C1 00 V1.0, 2003-07
Part Number & Organization
128MB 256MB 256MB 512MB x 64 -6 HEX C1 75 70 00 00 48 30 48 2A 75 75 45 45 00 3C 48 30 2D 55 00 00 E8 C1 00 x 64 -6 HEX C1 75 70 00 00 48 30 48 2A 40 75 75 45 45 00 3C 48 30 2D 55 00 00 01 C1 00 x 72 -6 HEX C1 75 70 00 00 48 30 48 2A 40 75 75 45 45 00 3C 48 30 2D 55 00 00 13 C1 00 x 64 -6 HEX C1 75 70 00 00 48 30 48 2A 40 75 75 45 45 00 3C 48 30 2D 55 00 00 02 C1 00
1 Rank 1 Rank 1 Rank 2Ranks 2Ranks
Byte# 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 to 40 41 42 43 44 45 46 to 61 62 63 64 65 to 71
Description Component Attributes -- tCK @ CLmax -0.5 (Byte 18) 7.5 ns [ns] tAC SDRAM @ CLmax -0.5 0.70 ns [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin (ns) tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Bank tAS, tCS [ns] tAH, TCH [ns] tDS [ns] tDH [ns] not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used SPD Revision Checksum of Byte 0-62 (LSB only) not supported not supported 18 ns 12 ns 18 ns 42 ns 0.75 ns 0.75 ns 0.45 ns 0.45 ns -- 60 ns 72 ns 12 ns 0.45 ns 0.55 ns -- Revision 0.0 --
128 MByte/ 256 MByte 20
JEDEC ID Code for Infineon -- JEDEC ID Code for Infineon --
Data Sheet
25
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C Unbuffered DDR SDRAM Modules
SPD Contents Table 12 SPD Codes for PC2700 Modules "-6" (cont'd) HYS64D16301HU-6-C HYS64D32300HU-6-C HYS72D32300HU-6-C HYS64D64320HU-6-C HYS72D64320HU-6-C 512MB x 72 -6 HEX xx 37 32 44 36 34 33 32 30 48 55 36 43 20 20 20 20 20 20 xx xx xx xx xx 00 V1.0, 2003-07
Part Number & Organization
128MB 256MB 256MB 512MB x 64 -6 HEX xx 36 34 44 31 36 33 30 31 48 55 36 43 20 20 20 20 20 20 xx xx xx xx xx 00 x 64 -6 HEX xx 36 34 44 33 32 33 30 30 48 55 36 43 20 20 20 20 20 20 xx xx xx xx xx 00 x 72 -6 HEX xx 37 32 44 33 32 33 30 30 48 55 36 43 20 20 20 20 20 20 xx xx xx xx xx 00 x 64 -6 HEX xx 36 34 44 36 34 33 32 30 48 55 36 43 20 20 20 20 20 20 xx xx xx xx xx 00
1 Rank 1 Rank 1 Rank 2Ranks 2Ranks
Byte# 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 to 98
Description Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Module Manufacturing Date -- Year Module Manufacturing Date -- Week Module Serial Number -- --
99 to 127 not used
Data Sheet
26
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C Unbuffered DDR SDRAM Modules
SPD Contents
Table 13
SPD Codes for PC3200 Modules "-5" HYS64D16301HU-5-C HYS64D32300HU-5-C HYS72D32300HU-5-C HYS64D64320HU-5-C HYS72D64320HU-5-C x 72 -5 HEX 80 08 07 0D 0A 02 48 00 04 50 50 02 82 08 08 01 0E 04 1C 01 02 20 C1 60 V1.0, 2003-07
Part Number & Organization
128MB 256MB 256MB 512MB 512MB x 64 -5 HEX 80 08 0D 09 01 40 00 04 50 50 00 82 10 00 01 0E 04 1C x 64 -5 HEX 80 08 07 0D 0A 01 40 00 04 50 50 00 82 08 00 01 0E 04 1C x 72 -5 HEX 80 08 07 0D 0A 01 48 00 04 50 50 02 82 08 08 01 0E 04 1C x 64 -5 HEX 80 08 07 0D 0A 02 40 00 04 50 50 00 82 08 00 01 0E 04 1C 1 Rank 1 Rank 1 Rank 2Ranks 2Ranks
Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type DDR-I = 07h # of Row Addresses # Number of Column Addresses # of DIMM Banks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] 128 256 13 9/10 1/2 x 64/x 72 0 SSTL_2.5 5 ns 0.50 ns
DDR SDRAM 07
DIMM Configuration Type (non- / ECC) nonECC/ECC Refresh Rate Primary SDRAM width Error Checking SDRAM width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM CAS Latency Self-Refresh 7.8 s x 16/ x 8 na/ x 8
tCCD = 1 CLK
2, 4 & 8 4 CAS latency = 2, 2.5, 3 CS latency = 0 Write latency = 1 unbuffered -- 6.0 ns
19 20 21 22 23
CS Latency WE (Write) Latency DIMM Attributes Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns]
01 02 20 C1 60
01 02 20 C1 60
01 02 20 C1 60
01 02 20 C1 60
Data Sheet
27
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C Unbuffered DDR SDRAM Modules
SPD Contents Table 13 SPD Codes for PC3200 Modules "-5" (cont'd) HYS64D16301HU-5-C HYS64D32300HU-5-C HYS72D32300HU-5-C HYS64D64320HU-5-C HYS72D64320HU-5-C x 72 -5 HEX 50 75 50 3C 28 3C 28 40 60 60 40 40 00 37 41 28 28 50 00 00 10 C1 00 xx 37 32 44 36 34 V1.0, 2003-07
Part Number & Organization
128MB 256MB 256MB 512MB 512MB x 64 -5 HEX 50 75 50 3C 28 3C 28 20 60 60 40 40 00 37 41 28 28 50 00 00 E4 C1 00 xx 36 34 44 31 36 28 x 64 -5 HEX 50 75 50 3C 28 3C 28 40 60 60 40 40 00 37 41 28 28 50 00 00 FD C1 00 xx 36 34 44 33 32 x 72 -5 HEX 50 75 50 3C 28 3C 28 40 60 60 40 40 00 37 41 28 28 50 00 00 0F C1 00 xx 37 32 44 33 32 x 64 -5 HEX 50 75 50 3C 28 3C 28 40 60 60 40 40 00 37 41 28 28 50 00 00 FE C1 00 xx 36 34 44 36 34 1 Rank 1 Rank 1 Rank 2Ranks 2Ranks
Byte# 24 25 26 27 28 29 30 31 32 33 34 35 36 to 40 41 42 43 44 45 46 to 61 62 63 64 65 to 71 72 73 74 75 76 77 Data Sheet
Description tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns] tAC SDRAM @ CLmax -1 [ns] tRPmin (ns) tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Bank tAS, tCS [ns] tAH, TCH [ns] tDS [ns] tDH [ns] not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used SPD Revision Checksum of Byte 0-62 (LSB only) JEDEC ID Code for Infineon JEDEC ID Code for Infineon Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4 Part Number, Char 5 0.50 ns 7.5 ns 0.50 ns 15 ns 10 ns 15 ns 40 ns 128 MByte/ 256 MByte 0.60 ns 0.60 ns 0.40 ns 0.40 ns -- 55 ns 65 ns 10 ns 0.40 ns 0.50 ns -- Revision 0.0 -- -- -- -- -- -- -- -- --
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C Unbuffered DDR SDRAM Modules
SPD Contents Table 13 SPD Codes for PC3200 Modules "-5" (cont'd) HYS64D16301HU-5-C HYS64D32300HU-5-C HYS72D32300HU-5-C HYS64D64320HU-5-C HYS72D64320HU-5-C x 72 -5 HEX 33 32 30 48 55 35 43 20 20 20 20 20 20 xx xx xx xx xx 0 V1.0, 2003-07
Part Number & Organization
128MB 256MB 256MB 512MB 512MB x 64 -5 HEX 33 30 31 48 55 35 43 20 20 20 20 20 20 xx xx xx xx xx 0 x 64 -5 HEX 33 30 30 48 55 35 43 20 20 20 20 20 20 xx xx xx xx xx 0 x 72 -5 HEX 33 30 30 48 55 35 43 20 20 20 20 20 20 xx xx xx xx xx 0 x 64 -5 HEX 33 32 30 48 55 35 43 20 20 20 20 20 20 xx xx xx xx xx 0 1 Rank 1 Rank 1 Rank 2Ranks 2Ranks
Byte# 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 to 98
Description Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
99 to 127 not used
Data Sheet
29
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C Unbuffered DDR SDRAM Modules
Package Outlines
5
0.1 A B C
Package Outlines
133.35 128.95 2.7 MAX. A
1)
0.15 A B C
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
B 0.4
C
1.27 0.1 49.53
64.77 95 x 1.27 = 120.65
3.8 0.13
1.8 0.1 93
0.1 A B C
184
10 17.8
L-D IM-184-18
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
1) On ECC modules only Burr max. 0.4 allowed
Figure 7 Package Outlines - Raw Card C (128 MByte, 1 Rank Module)
Data Sheet
30
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 2.7 MAX.
1)
A
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
B 0.4 1.27 0.1 49.53 95 x 1.27 = 120.65 C 64.77 1.8 0.1 93 0.1 A B C 184
3.8 0.13
10
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
1) On ECC modules only Burr max. 0.4 allowed
L -D IM - 1 8 4- 3 0
Figure 8
Package Outline - Raw Card A (256 MByte, 1 Rank Module, -5 and -6, ECC)
Data Sheet
31
V1.0, 2003-07
17.8
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 4 MAX.
1)
A
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
BC 0.4 1.27 0.1 49.53 95 x 1.27 = 120.65 64.77 1.8 0.1 93 0.1 A B C 184
3.8 0.13
10
3 MIN.
Detail of contacts
1)
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
1) On ECC modules only Burr max. 0.4 allowed
Figure 9 Package Outline - Raw Card B (512 MByte, 2 Rank Module, -5 and -6, ECC)
17.8
L -D IM - 1 8 4- 3 1
Data Sheet
32
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 2.7 MAX.
A
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
B 0.4
C
1.27 0.1 49.53
64.77 95 x 1.27 = 120.65
3.8 0.13
1.8 0.1 93
0.1 A B C
184
10 17.8
L-D IM-184-32
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Figure 10 Package Outline - Raw Card A (256 MByte, 1 Rank Module, -5 and -6, Non ECC)
Data Sheet
33
V1.0, 2003-07
HYS[64/72]D[16x01/32x00/64x20]HU-[5/6]-C Unbuffered DDR SDRAM Modules
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 4 MAX.
A
4 0.1
1 2.36 0.1
o0.1 A B C
6.62 2.175 6.35
92
31.75 0.13
BC 0.4 1.27 0.1 49.53 95 x 1.27 = 120.65 64.77 1.8 0.1 93 0.1 A B C 184
3.8 0.13
10
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
L-D IM-184-33
Figure 11
Package Outline - Raw Card B (512 MByte, 2 Rank Module, -5 and -6, Non ECC)
Data Sheet
34
V1.0, 2003-07
17.8
www.infineon.com
Published by Infineon Technologies AG

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